Ultra large scale integrated (ULSI) circuits technology has produced a variety of electronic devices such as dynamic random access memory, static random access memory, electrically erasable and programmable read only memory, and logic devices with minimum design rule of 0.35 μm. Low resistivity interconnect materials are required for future front-end and back-end of line interconnect materials, and low permittivity interlayer dielectrics will be required. The narrowness of contacts and vias is mainly a result of transistor scaling and the need for higher interconnect packing density. Salicide structures for both gate and source/drain regions are necessary to reduce the gate resistance of the dual gate CMOS as well as the source/drain resistance. Aluminum (Al) is the most commonly used interconnect material in ULSIs, since it has many advantages such as low resistivity, adhesion to insulators, chemical stability due to self-passivation by thin Al oxide.