ABSTRACT
Currently, there is a wide variety of neural network models, and the most mainstream neural network models include deep neural networks (DNNs), convolutional neural networks (CNNs), and long short-term memories (LSTMs). LSTM, known for its intrinsic temporal properties, has been applied in the fields of speech recognition, semantic analysis, image recognition, etc. The characteristics of LSTM networks are the presence of a large number of connections, huge parameter sizes, and a complex computational process. Achieving high performance and low power consumption in LSTM neural networks is one of the hot issues in both academia and industry. Utilizing low-power hardware to implement neural network accelerators presents an effective solution. Field-programmable gate array’s (FPGA) high performance and low power consumption make it widely used as a hardware acceleration. In this chapter, we design and implement a hardware accelerator for LSTM neural network prediction algorithms based on FPGA. First, the background of hardware acceleration of neural networks is briefly described in Section 9.1, followed by an introduction to the algorithm principles of recurrent neural networks (RNNs). Finally, we discuss the customization and optimization details of RNNs on the FPGA platform.
