ABSTRACT
A circuit for the clock signal generation or recovery is often required to achieve accurate data transfer between the different building blocks (see Figure 6.1) of very large-scale ICs operating at high speed. In the case of transmission systems, as shown in Figure 6.2, the multiplexer converts the input data into a serial stream of non-return-to-zero data, which then drives a high-speed buffer. At the receiver, the signal level is determined by an amplifier and the clock signal is recovered from the transmitted data and used to control the demultiplexer. The resulting data synchronization determines the accuracy of the information regeneration. The rising edges of the clock signal, whose frequency is set equal to the data rate, should coincide with the midpoint of each data bit, such that the sampling occurs farthest from the preceding and following transitions, yielding a maximum tolerance margin for the jitter and other timing uncertainties.
