ABSTRACT
This chapter discusses the layout technique and packaging information. For a specific circuit, a layout specifies the position and dimension of the different layers of materials as they would be laid on the silicon wafer. However, the layout description is only a symbolic representation, which simplifies the description of the actual fabrication process. Some of the main layers used in any layout description are n-diffusion, p-diffusion, poly, metal-1, and metal-2. Each of these layers is represented by a polygon of a particular color or pattern. Process-induced damage to the thin gate oxide occurs when conductors charge up during wafer fabrication. Conductor layers that are exposed to a plasma environment during processing will charge up and cause a current to be passed through any gate-oxide areas that are electrically connected to the exposed conductor layers through lower conductor layers.
