ABSTRACT
From a designer's point of view, this chapter provides brief information about the problem and rectification of the known issues associated with the very-large-scale integration (VLSI) interconnect. The objectives of this chapter are to make aware the reader about the evolution of interconnects, scaling problems, electrical modeling, and extraction of interconnect parasitics. Additionally, this chapter provides a general perspective related to interconnect model (ABCD parameters, finite difference time domain (FDTD) approach, etc.) such that the readers can use this concept to design and mitigate the interconnect problem at the nanolevel for next-generation VLSI.
