ABSTRACT
The SiGe source/drain stressor (e- SiGe) technique has emerged as a performance booster for advanced technology nodes. In this chapter, an extensive 3D TCAD simulation framework has been used to demonstrate how the elastic stress models can be applied for the simulation of stress transfer using source/drain SiGe -epi layer for p-FinFETs. In deeply scaled technologies, process and environment variations become the important sources of variabilities. Thus, the design and optimization of FinFETs at the nanoscale including variability are extremely challenging. Metal grain granularity (MGG) and random discrete dopants (RDDs) are the major sources of process-induced variability in FinFETs. In this chapter, the device critical performance parameters such as threshold voltage, Ion, Ioff, subthreshold slope variation due to RDD, and MGG are examined in detail. The impact of location-dependent discrete dopants in different positions such as the source/drain side has been studied to predict the electrical performance.
