ABSTRACT
This chapter introduces the ARM Cortex-M CPU architecture first and then introduces the Real Time-Thread interrupt management mechanism in conjunction with the Cortex-M CPU architecture. The program status word registers store arithmetic and logic flags, such as negative flags, zero flags, overflow flags, and so on. The interrupt mask register bank controls when to disable the Cortex-M interrupts. Cortex-M introduces the concept of operating modes: Thread mode and Handler mode. PendSV, also known as the suspendable system call, is an exception that can be suspended like a normal interrupt. PendSV exceptions are initialized as the lowest-priority exceptions. Each time a context switch is required, the PendSV exception is triggered manually, and the context switch is performed in the PendSV exception handler. The interrupt vector table is the entry point for all interrupt handlers.
