ABSTRACT
It has been noted that there has been a serious energy and power shortage throughout the world in recent years. The natural resources of the planet might not last very long. It has to disappear eventually. In light of such a significant issue, the idea of GC comes to mind. This chapter represents progress for the GCC industry. In this chapter, a low-power finite impulse response (FIR) filter model is designed utilizing the Kintex-7 device. To optimize the power consumption of the FIR filter on the FPGA device, high-speed transceiver logic (HSTL) input output (IO) is used. From the power analysis, it has been observed that the device consumes optimal power when the impedance matching for the FIR filter is matched with HSTL_II IO. The devices give maximum power dissipation when the impedance is matched with HSTL_I_18 IO.. There is a change of 108.705% in TPC for HSTL_II (Optimal) to HSTL_I_18 (Maximum) IO.
