ABSTRACT
It has been observed that in past few years the globe is facing huge problem of energy and power deficiency. The earth’s natural resources may not live long. Someday it has to be vanished. In the context of such a huge problem, the idea of GC comes in people’s mind. This chapter is a step in the area of GCC. In this chapter, a power-efficient model of packet counter is designed with the help of Kintex-7 device. To optimize the power utilization of packet counter, in this chapter, the authors have used the impedance matching technique, for which they have used the MOBILE DDR IO standards. In FPGA IO, standards are used to match the input and output impedance of the circuit. In this chapter, the TPC of the device is observed for a different set of frequency values for the MOBILE DDR IO. It is observed that the TPC of the device increases as the frequency of operation increases. The device gives optimal power for 100 MHz frequency value, and the device consumes the maximum power for the frequency of 5 GHz.
