ABSTRACT
In the age of growing technologies, the globe is much concerned about energy and power deficiency. This chapter highlights making the things suitable for green communication (G Comm.). In this chapter, a power-efficient design of UART (Universal Asynchronous Receiver Transmitter) is implemented on FPGA device. The implementation of the UART is done on VIVADO Design Suite, and the results are observed on Kintex-7 FPGA. To optimize the power consumption of the UART on the FPGA device, low-voltage complementary metal-oxide (LVCMOS) input output (IO) is used. IO standards are used in FPGA to match the impedance so that the power consumption is optimized. In this chapter, the optimized power is observed for LVCMOS 25 and LVCMOS 33 IO standards as compared to the other LVCMOS IO standards. There is an increment in power consumption when the TP consumption is compared between LVCMOS 25, LVCMOS 33 IO standard and LVCMOS 12, LVCMOS 15 IO standard, which is an increment of 0.619%. The TP consumption increment is 0.826% for LVCMOS 18 IO standard.
