ABSTRACT
This chapter describes a field programmable gate array (FPGA)-based method for on-board detection and matching. A pipeline structure and a parallel computation are introduced. A model which combines the modified speed-up robust feature (SURF) detector, and a binary robust independent elementary features (BRIEF) descriptor is described. During the process of implementation, (1) a computation through the overflow technique is used to reduce bit width of integral image, and a right shift operation is used instead of a divider; (2) the responses of Hessian matrix in different scales are computed in parallel. The parallel processing also can be found in the 74 comparators in 3D non-maximal suppression module, the 256 comparators in BRIEF generator module and 100 comparators in matching module.
Three pairs of images with different land coverages are applied to evaluate the performance of FPGA-based implementation. The experimental results demonstrate that (1) when the image pairs consist of artificial features, such as buildings and roads, the performance from FPGA-based implementation is very close to that from the PC-based implementation. When the image pairs consist of natural features, such as woods, the performance from FPGA-based implementation is worse; (2) the FPGA-based implementation can achieve a 304 fps under a 100 MHz clock frequency, which is as about 27 times fast as that from PC-based implementation.
