ABSTRACT
Power integrity (PI) is the scientific field of analyzing and designing the power distribution network (PDN) from VRMs to the ASICs. The main PI-related activity for hardware designers is the decoupling capacitor value/quantity selection for the schematic, PCB design (fanout, placement, planes, and stackups), VRM output impedance tuning, and design validation. The ASIC datasheets require the local voltage at the power pins at any moment to remain within a tight tolerance band relative to the nominal value. Due to design imperfections, this voltage tends to deviate and may go over the tolerance limits in a static or dynamic way. Our objective is to prevent that.
