ABSTRACT
This chapter examines potential future hardware advancements, and how the application developer may prepare for those hardware advancements. Skylake is expected to be built on a 14 nm manufacturing process and come with more cores than previous Intel Xeon CPUs. The first primary trend that can be seen from looking at future hardware designs shouldn't seem all that surprising or new. The second primary trend describes the combined vector unit width of physical CPUs, not the ISA itself – e.g., two 512-bit SIMD units are counted as a CPU vector width of 1024 bits. Finally, the third trend found in future hardware designs is the increasing complexity of the memory hierarchy, as additional levels such as L4 caches and high-bandwidth memories are added. The growth of CPU vector widths is expected to continue into the foreseeable future, so optimizing application codes to be amenable to long vector lengths, where possible, is highly recommended.
