ABSTRACT
When computer designers build hardware for float arithmetic, they also allocate room to perform the multiplication of the fraction to twice as many bits as the fraction length. To do that quickly means being able to do all the partial products at once in the “parallelogram” for a multiply, and then collapse the sum with a double-length accumulator. For example, a simple 8-bit by 8-bit multiplier that produces an 8-bit rounded result can be envisioned like this, the binary version of the way people do pencil-and-paper multiplication with decimals:
The bits shown in light blue are never shown to the user; they are part of the hidden scratchpad. (Some computers have instructions for retrieving the low-order half of the bottom-line product, however, for doing things like extended-precision arithmetic). There are similar structures for doing floating point addition and subtraction (where the bits must usually be shifted first because their exponents put their binary point in different places), divides, and square roots. If the rules for rounding are well defined, all computers will return the same result. There are no compatibility problems and no surprises.
