ABSTRACT
X iao Sun and T. P. M a Electrical Engineering Department, Yale University, New Haven, CT 06511, USA xiao.sun@ yale.edu, t. ma@yale.edu
In this chapter, w e in trod u ced a few novel e lectrica l characterization m ethods for studying m odern tran sistors, w ith a focus on investigating various traps in the tran sisto r’s gate stacks, and the resu lting tran sisto r degradation. It is w idely believed th a t nanoscale tran sisto rs m ade on nonsilicon su bstrates, such as SiGe, Ge, and III-V sem iconductors, will be adapted a t or beyond the 7 nm node. Traps a t the in terface as w ell as in the gate stack will p resen t great challenges for th ese advanced tran sistors.
