ABSTRACT
This chapter covers three important technology topics related to the design of SUM devices. These are the preferred selection of dielectric films applicable to SUM devices, technology integration considerations related to the fabrication of SUM devices, and associated stack design considerations related to achieving the desired device properties. Most higher performance SUM devices are either derivatives of DTMs or employ band-engineered progressive band offset (PBO) stack designs to enhance internal field aided carrier transport. Metal gate interface layer is a critical technology item for both FET device design and nonvolatile memorie (NVM) device gate stack design. The preferred layers are either TiN or TaN with characteristics of compatibility and desired higher work function requirements for advanced CMOS technology. Therefore, for SUM technology, such interface layer should be assumed unless specific options are discussed.
