ABSTRACT
This chapter discusses in the context of tunnel-based floating gate (FG) and charge-trapping (CT) devices employing conventional gate stack designs as explained in earlier sections. It explores charge retention strictly in the context of charge transport within the dielectric layers of the nonvolatile memories (NVMs) device stack. The various potential charge leakage modes are identified in the band diagram as current components. Silicon based NVM devices, as explained in the beginning, are a variation in an FET device, whereby electronic charges are stored in the gate insulator stack to create multiple relatively stable threshold states called memory states. Memory retention and simply called "Retention" is perhaps the most important device parameter distinguishing NVM devices from other types of memory devices, such as, DRAM. Electrostatic potential created by stored charges establish significant field across either the silicon substrate or across the control gate of the device.
