ABSTRACT
This chapter implements synchronous sequential machine designs using Verilog hardware description language. The designs will be accomplished by utilizing built-in primitives, dataflow modeling, behavioral modeling, structural modeling, or a combination of these modeling techniques. The state of a synchronous register is usually a direct result of the input vector, whose binary variables connect to the flip-flop data inputs, either directly or indirectly through δ next-state logic. Most registers are used primarily for temporary storage of binary data and do not modify the data internally; that is, the state of the register is unchanged until the next active clock transition. A parallel-in, serial-out register accepts binary input data in parallel and generates binary output data in serial form. The binary data can be shifted either left or right under control of a shift direction signal and a clock pulse, which is applied to all flip-flops simultaneously.
