ABSTRACT
This chapter implements synchronous sequential machine designs using Verilog hardware description language (HDL). The designs will be accomplished by utilizing built-in primitives, dataflow modeling, behavioral modeling, structural modeling, or a combination of these modeling techniques. The chapter describes techniques for error detection for synchronous sequential machines. An error in a synchronous sequential machine may alter the δ next-state function, the λ output function, or both. The chapter describes a general block diagram for a synchronous sequential machine using multiplexers for the δ next-state logic. The combinational logic which connects to the input of the multiplexer array is either very elementary or nonexistent. Programmable logic devices (PLDs) can be used in applications involving the synthesize of synchronous sequential machines using traditional techniques. The chapter presents the synthesize PLDs using Verilog HDL and illustrates the use of PLDs in the synthesis of combinational logic and synchronous sequential machines.
