ABSTRACT
This chapter implements asynchronous sequential machine designs using Verilog hardware description language. The designs will be accomplished by utilizing one or more of the following modeling methods for each design: built-in primitive gates, dataflow modeling, behavioral modeling, and structural modeling. The chapter provides examples which illustrate the synthesis procedure for asynchronous sequential machines using a timing diagram and/or a verbal specification. The traditional synthesis procedure is used in designing the asynchronous sequential machines. The sum-of-products form will be used in the implementation of the asynchronous sequential machine, since the product-of-sums equation requires additional logic gates. The chapter shows the design module for the asynchronous sequential machine using built-in primitives. It also shows the test bench module, which displays the timing diagram for the input variables and the output variable. Using different design methodologies illustrates alternative methods to design identical asynchronous sequential machines.
