Synthesis of Pulse-Mode Asynchronous Sequential Machines Using Verilog HDL

This chapter implements pulse-mode asynchronous sequential machine designs using Verilog hardware description language. The designs will be accomplished by utilizing one or more of the following modeling methods for each design: built-in primitive gates, dataflow modeling, behavioral modeling, and structural modeling. Dataflow modeling method is at a higher level of abstraction than gate-level modeling using built-in primitives. Behavioral modeling method describes the behavior of a digital system and is not concerned with the direct implementation of logic gates but more on the architecture of the system. This is an algorithmic approach to hardware implementation and represents a higher level of abstraction than the previous modeling methods. A Verilog module that is designed using behavioral modeling contains no internal structural details, it simply defines the behavior of the hardware in an abstract, algorithmic description. Verilog contains two structured procedure statements or behaviors: initial and always.