ABSTRACT
As the silicon industry moves toward the end of the technology roadmap, providing cost-effective and power-efficient system-on-chip memory solutions has become ever more challenging. While there are increasing demands for embedded memory capacity, conventional embedded working memories such as embedded static (SRAM) and dynamic random-access memory (DRAM) have been facing scalability challenges along with increasing static leakage power. The static leakage power consumption of embedded working memories, particularly in the case of high-performance mobile chips, accounts for a substantial portion of total power consumption, which is expected to strengthen at future technology nodes. Considering that embedded memory accounts for more than 50% of the total chip area of commercial state-ofthe-art mobile chipsets, it is important to develop an alternative embedded memory technology that can overcome these challenges without compromising the benefits of conventional working memories.
