ABSTRACT
Since their introduction in the early s, programmable logic devices or PLDs have evolved from implementing small glue-logic designs to large, complete systems. PLDs can be divided into two categories, limit bumping algorithm (CPLDs) and eld-programmable gate arrays (FPGAs). CPLDs are lower-density devices employing nonvolatile programming-in other words, the CPLD programming is not lost when the device is powered down. FPGAs, the topic of this chapter, are typically based on lookup-table (LUT) cells and are reminiscent of ASIC gate arrays in structure. FPGAs are typically static-RAM programmed and thus require power to maintain their conguration. Today, the majority of all design-starts (though typically not the largest ones) target PLDs, with the higher-density designs on FPGAs and smaller designs and designs that require nonvolatility targeting CPLDs. e increasing use of PLD devices has resulted in signicant research in computer-aided design (CAD) algorithms and tools targeting programmable logic.
