ABSTRACT
This chapter presents several examples of functional decomposition that are designed using Verilog hardware description language (HDL). It discusses the theory and design of iterative networks which are useful in many applications such as adders, comparators, array multipliers, and single-bit detection circuits. The chapter explains the concept of Hamming code by providing more detailed information and presents the cyclic redundancy check (CRC) code for error detection and correction by implementing these unique devices with linear feedback shift registers. It also presents residue checking and parity prediction which are useful techniques in detecting errors in adders. The chapter introduces a method to determine the condition codes of sum < 0, sum = 0, and sum > > 0 before the actual sum is obtained. Finally, it presents two examples of designing arithmetic and logic units (ALUs) using Verilog HDL: 4-function ALU by using structural modeling; and 8-function ALU by using behavioral modeling.
