Combinational Logic Design Using Verilog HDL

This chapter introduces the Verilog hardware description language (HDL) which will be used to design combinational logic. Designs can be modeled in three different modeling constructs: dataflow, behavioral, and structural. The chapter presents a design methodology that is characterized by a low level of abstraction, where the logic hardware is described in terms of gates. Designing logic at this level is similar to designing logic by drawing gate symbols; there is a close correlation between the logic gate symbols and the Verilog built-in primitive gates. Each predefined primitive is declared by a keyword such as and, or, nand, and nor. A structural module may contain behavioral statements, continuous assignment statements, built-in primitives, user-defined primitives (UDPs), design modules, or any combination of these objects. Design modules can be instantiated into a higher-level structural module in order to achieve a hierarchical design.