Programmable Logic Devices

This chapter illustrates the use of programmable logic devices (PLDs) in the synthesis of combinational logic and synchronous sequential machines. The PLDs are: programmable read-only memories (PROMs), programmable array logic (PAL) devices, programmable logic array (PLA) devices, and field-programmable gate arrays (FPGAs). The chapter describes the organization and operation of a generalized FPGA and concludes with a synthesis example for a Moore machine. The organization of a typical FPGA consists of a matrix of identical logic block elements encompassed by a perimeter of input/output (I/O) blocks. The combinational function utilizes a memory table-lookup technique which can be programmed to implement any Boolean function of the input variables. The output of the combinational function connects to the storage elements. The output signals can be programmed to be a function of either the storage elements only or the storage elements and the present inputs, providing characteristics that are consistent with both Moore and Mealy machines.