ABSTRACT
Over the past 40 years [1-7], to improve MOSFET performance, strain introduced via biaxial tensile
stress using a Si-SiGe heterostructure has received substantial attention. Little attention, however, has
been paid to uniaxial stress created via heterostructures [8]. Both biaxial and uniaxial stress offer large
enhanced electron and hole mobility and great potential to continue Moore’s law when conventional
scaling slows. Since biaxial tensile stress introduces advantageous strain for both n-and p-type
MOSFETs, it has potential importance to CMOS logic technologies. However, biaxial stress has not
yet been adopted into high-volume manufacturing due to cost and integration complexity. The use of
uniaxial stress for CMOS logic is not without its own complexities, as will be described in Chapter 21,
but has been adopted at the 90 nm technology generation [8-10] including heteroepitaxy introduced for
the first time in commercial CMOS chips.
