Industry Examples at the State-of-the-Art: Intel's 90nm Logic Technologies

This chapter describes uniaxial strained Si and Si1xGex heteroepitaxy introduced for the first time at the 90 nm technology generation into high-volume manufacturing. For more than 30 years,

CMOS device technologies have improved at a dramatic rate due to dimension scaling. Scaling

the vertical and horizontal MOSFET dimension reduces channel resistance through increased inversion

charge and lower source to drain resistance, respectively. It is this unique property of higher perform-

ance and lower cost through dimension scaling that has established the MOSFET as the clearly dominant

solid-state device. The semiconductor and microelectronic industry has made remarkable and

nearly unprecedented progress during the last 30 years. During this time, the MOSFET gate length

scaled from 10mm to 45 nm and now contains many features at the nanoscale. Figure 21.1 shows

the evolution pictorially with Lilenfield’s MOSFET concept, the first experimental transistor in 1947,

and the present day 45 nm transistor which incorporates Si1xGex in the source and drain to strain the Si channel [1-3].