To gain insight into the advantages of partial dynamic reconfiguration, let us introduce the following motivational example. Consider a simple FPGA with three reconfigurable units and an application represented by the task graph shown in Figure 3.1(a) (where a node with label n/m has a latency of n cycles and needs m reconfigurable units). The time partitioning approach

Figure 3.1: A reconfigurable device (a), a program specification (b), the time partitioning schedule (c), and the optimal schedule (d).