ABSTRACT
In the previous chapter we discussed the basics of instruction set architecture and datapath and contr ol unit design. By now , the r eader should have a good understanding of the essentials of central processing unit (CPU) architecture and implementation; you may even feel (the author dar es to hope) that, given enough time, you could generate the logical design for a complete, usable CPU. Once upon a time, that would have been a good enough product to sell. Now, however, to succeed in the marketplace a pr ocessor (and the system containing it) must not only work, but must perform extr emely well on the application of inter est. This chapter is devoted to exploring implementation techniques that manufacturers have adopted to achieve the goal of making their CPUs pr ocess information as rapidly as possible. The most ubiquitous of these techniques is known as
pipelining
. As we shall see, almost all high-performance computers utilize some form of pipelining.
