ABSTRACT
This chapter provides a brief introduction to the design methodologies and modeling constructs of the Verilog hardware description language (HDL). Modules and ports will be presented. Modules are the basic units that describe the design of the Verilog hardware. Ports allow the modules to communicate with the external environment; that is, other modules and input/output signals. Different methods will be presented for designing test benches. Test benches are used to apply input vectors to the module in order to test the functional operation of the module in a simulation environment.
