The primary design trends are concerned with packing the greatest amount of circuitry in the smallest possible area and reducing parasitic circuit effects. The dynamic RAM or DRAM will be used as an illustrative example of future technological projections. Specifically, the International Solid State Circuits Conference (ISSCC) technical papers from 1983 and 1992 will be used for comparative purposes and upon which to draw conclusions and future projections. It should be realized that there is a time lag of 3 to 6 years from the time a DRAM at a specific level of integration is formally presented at ISSCC to when products of that level of integration are available at a production rate of 10 million units per month or greater (Fig. 5.1). It is anticipated that this time delay will increase for future generations of DRAMs.