ABSTRACT
This chapter discusses the design and analysis of complementary metal-oxide-semiconductor field-effect transistor (CMOS) sequential logic circuits and introduces two basic CMOS memory elements, the D-latch and the D-flip-flop. It focuses on the design and analysis of synchronous sequential logic circuits and deals with synchronous sequential circuits, the D-latch is nevertheless an asynchronous sequential circuit. The chapter also deals with a simple example to review the general design process of sequential circuits. A sequential logic circuit can operate with or without the control of a clock signal. The basic memory element employed in a CMOS sequential logic circuit is the D-latch. In the case of a synchronous sequential logic circuit, one can adjust the clock speed to capture the new state only after all state variable bits settle down so that delay variations cause no hazard. A memory element can be built by setting up an asynchronous sequential logic circuit that has self-sustaining stable states.
