ABSTRACT
In this chapter, author discusses key challenges in designing Flash memories. Scaling the tunnel oxide thickness in nonvolatile memories (NVMs) is examined. Semiconductor memory can be divided into two categories, volatile memory and NVM. In volatile memory, the information is saved only as long as the system power is on. Metal–oxide–semiconductor field-effect transistors employing programmable floating gates have drawn much attention in the semiconductor memory industry. In one of its memory states biases on emitter and anode electrodes were ramped up to 1.2 V, and ramping the bias on drain electrode up to 1.2 V flips the memory state of the cell. SRAM remains the most cost-effective embedded memory solution for many such applications and could be made possible by continued advances in metal-oxide-semiconductor device scaling. A predictive technology model needs to be developed for scaled SRAM in the 90–22 nm technology nodes. The 6T SRAM cell design has so far been successfully scaled in bulk and silicon-on-insulator technologies.
