ABSTRACT
The development of threedimensional integrated circuits (3D ICs) with through silicon vias (TSVs) has provided a promising platform to satisfy the
development in accordance with Moore’s law. The Cu filler material used in TSVs plays an important role in providing the desired quality of TSVs. Cu pro vides lower stress, voidfree filling, and good thermal cycling performance, conductivity, and electrical currentcarrying capability [2]. Some of the other TSV filler materials used are conductive polymer pastes, gold (Au), polysili con, and tungsten (W) [3-5]. However, there are issues of testing, packaging, and fabrication of these filler materials. The development of a 3D IC with Cubased TSVs from twodimensional integrated circuits (2D ICs) is shown in Figure 3.1. TSVs provide electrical connections between oxide or through silicon tiers in vertical directions. They decrease the distance between connec tions and thus provide reduced signal delay and power consumption, higher bandwidth, and compact and reliable connection paths along with easing design complexities. It is important to discuss the various aspects of Cubased TSVs because Cu is the most common filler material because of its economic feasibility and excellent electrical properties.