Architecture of the On-Chip Processing Elements

This chapter describes the architecture organization and methods for functional customization of the on-chip programmable processing elements (PEs) of the field of configurable resources. There are different methods for implementing the arithmetic–logic functions in the fine-grained PEs and complex macro functions in the coarsegrained PEs. The most complicated application-specific macro functions usually require hybrid organization of PEs. These types of PEs contain the general-purpose reduced instruction set computing processing core combined with application-specific hardware accelerator composed of fine-grained and coarse-grained PEs. In contrast to the fine-grained PEs, the coarse-grained PEs is configured for the macro function using control registers: operation mode registers or configuration registers. Each bit in this registers is associated with the control input of the mode-switching multiplexer. In contrast to the fine-grained PEs, the coarse-grained PEs is configured for the macro function using control register: operation mode registers or configuration registers.