ABSTRACT
This chapter describes the general organization of configuration memory hierarchy and the concept of hardware circuit virtualization illustrated by quantitative examples of reconfigurable computing system (RCS). The procedure of loading the configuration bit-stream to the on-chip configuration memory is conducted by an associated on-chip configuration controller via configuration port of the programmable logic device (PLD). The on-chip configuration controller could be a dedicated circuit dealing with the external controller-loader via special configuration port of the field programmable gate array or complex programmable logic device. Configuration management system being deployed in PLD and/or microcontroller should interact with system ports of the RCS providing communication with secondary storage. This is necessary to update existing set of configuration bit-files in the main configuration memory. The hierarchical organization of the configuration memory subsystem in RCS may give the same benefits as virtual memory organization in conventional computing architectures.
