ABSTRACT
The silicon-integrated circuit is one of the wonders of the twentieth century and the continuous advancement of microelectronics has revolutionized our way of life. Moore’s law predicted that the computing power of silicon chips would double every 18-24 months to keep up with the insatiable consumer demand for higher performance electronic products at lower cost. Over the past few decades, performance improvements have been achieved mostly through packing more transistors on a single chip and increasing the size of the silicon wafers. Shrinking of transistor size increases switching speed of the integrated circuits; however, it makes interconnections between transistors work slower. To date, the overall signal delay is no longer dominated by the intrinsic gate delay of the transistor, but greatly affected by the interconnect delay as well. Figure 28.1 is a schematic cross section of a silicon-integrated circuit (IC) including both front-end-of-the-line (FEOL) at the transistor level and back-end-of-the-line (BEOL after the fi rst metallization) in the multilevel interconnects. Low-dielectric constant material is used as the insulating material between metals in the BEOL. Reducing the dielectric constant of the insulating material is an effective method to mitigate interconnect delay.
