The use of high-quality strained-Si layers grown on relaxed-SiGe substrates or on an insulator holds a great promise to enhance conventional Si complementary metal oxide semiconductor (Si CMOS) technology. In order to fabricate MOSFETs on a Si substrate, conventionally a very thin layer of insulator is thermally grown or deposited on the Si substrate followed by a polysilicon gate electrode definition. With the advent of strained-Si1−xGex-based devices, it is important to consider some of the processing issues that separate these alloy layers from conventional Si substrate and conventional Si processing technology. One area of concern in the metal oxide semiconductor-based Si1−xGex technologies is the formation of high-quality surface passivation with low density of interface states.