As the end of the Si roadmap is approached, strained-Si channels offer a way to compensate for the reduction in MOSFET drive currents that accompany transistor scaling. Strain is an effective mechanism to modify the carrier transport properties of silicon. Strained-Si/SiGe MOSFETs take advantage of strain-induced changes of carrier transport in silicon and obtain current drive enhancements. The field has centered on process-induced strained-Si MOSFETs, because of its better compatibility with mainstream CMOS, and the impressive mobility enhancements that can be realized in that system at aggressively scaled gate lengths. Jankovic and O’Neill [1] have investigated the influence of strained-Si cap layers on n-p-n heterojunction bipolar transistors (HBTs) fabricated on virtual substrates. Using an approximate theoretical model, it has been shown that the presence of a strained-Si/SiGe (relaxed) heterojunction barrier in the emitter can substantially improve the current gain, relaxing the need for a high Ge content in the strained-SiGe base. Furthermore, two-dimensional numerical simulations of a virtual substrate HBT with a realistic geometry demonstrate that, besides the current gain enhancement, a three-times improvement in ft and fmax can be realized when a strained-Si/SiGe emitter is incorporated. Although high performance complementary heterojunction MOSFETs (HCMOS) using strained-Si channels fabricated on virtual substrates have been demonstrated [2], it is important that heterojunction bipolar transistors (HBTs) are also integrated together with HFETs for future Bi-HCMOS technology on virtual SiGe substrates.