ABSTRACT
Performance improvements for each new silicon CMOS technology generation have been driven mainly by geometric scaling, which implied increasing the channel doping concentration and vertical electrical field required to control short-channel effects. However, these two aspects of geometric scaling adversely affect carrier mobility due to impurity scattering and high-field saturation. Over the past decade, Technology CAD (TCAD) has become essential for developing and optimizing semiconductor process technologies ranging from nanoscale microprocessors to large-scale high-voltage power devices. TCAD is being increasingly used in manufacturing for advanced process control and parametric yield improvement. TCAD can lower technology development costs up to 40% by reducing the number of experimental lots and shortening development time. This is significant, considering the rising costs of product development and new wafer fabrication facilities. Process engineers are now struggling to integrate new materials and device structures into the process, often resulting in new physical effects such as process-induced stress, statistical dopant fluctuations, spatial quantization, and nonequilibrium transport. While in the past many of these effects could have been neglected, they are now primary considerations in developing a new process technology. With its physical basis, TCAD is capable of capturing detailed process effects, and calibrated TCAD flows can be used to generate computationally efficient process compact models (PCMs) that retain key processto-device correlations. Using PCMs, manufacturing engineers can analyze process sensitivity, and identify key process steps to improve overall process capability.
