After more than three decades of continued progress in CMOS devices technology, especially aggressive scaling in the last few years, the CMOS scaling is now approaching the fundamental limits. As we enter the nanometer regime, stress from standard process steps such as source/drain doping introduce significant stress in the channel of MOSFETs. With the continuing reduction of device dimensions, the impact of process-induced stress on device performance is becoming increasingly important. Besides scaling, several innovative mobility enhancement techniques are being attempted to maintain the CMOS performance improvement. Mobility enhancement is attractive because it improves device performance without device scaling. However, continued miniaturization increases device complexity and internal mechanical stress. The stress may cause dislocations, film cracking, and degradation of gate oxide quality. To reduce or avoid the buildup of stress during processing, it is important to identify the stress causing process steps, and locate high-stress areas with high spatial resolution.