Toward strained-Si engineering, during the last 15 years major focus has been on tensilely strained (biaxial) substrates as it is possible to improve both nand p-MOSFETs simultaneously. Although this is true, it occurs only at low electric field and high stress [1]. Currently, uniaxial stress has become the preferred method to strain the Si lattice and has been implemented into several 90-nm logic technologies [2, 3, 4]. Strain influences electrons and holes in CMOS transistors differently. Tensile strain, in which the interatomic distances in the silicon crystal are stretched, typically increases the mobility of electrons, making n-MOSFETs faster. But tensile strain may not benefit p-MOSFETs as much, and it may even slow them down. Compressive strain, in which those interatomic distances are shortened, produces essentially the opposite effects.