ABSTRACT
Digital signal processors (DSP) architectures have differed from mainstream processor architectures by having many irregularities and idiosyncrasies that are driven by the unique challenges to DSP computation. DSPs have tended to become very long instruction word architectures in recent years, as opposed to superscalar that most general purpose processors are. Because of a lack of good compilers and good support tools, most DSPs are still programmed manually in assembly language. For modeling DSP programs, dataflow models of computation have proven to be elegant and efficient. In summary, executing a dataflow specification of a DSP system involves two fundamental, processor-independent requirements: avoiding buffer underflow and avoiding unbounded data accumulation. The term "consistency" refers to the two essential requirements of DSP dataflow specifications–the absence of buffer underflow and of unbounded data accumulation. The dataflow graph specification of a DSP program has an underlying dataflow computational model that specifies the rules and restrictions on the manner in which actors execute.
