ABSTRACT
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The semiconductor industry has been rapidly developing, achieving 1-gigabyte (GB) dynamic random access memory (DRAM) early in the 21st century. As semiconductor chip size is scaled to submicron dimensions and additional levels are added to multilevel interconnection schemes, the required degree of planarization is increased. Though numerous planarization processes exist, including resist etch back, spin on glass (SOG), boro-phosphate-silicate glass (BPSG) reflow, and so on, chemical mechanical planarization (CMP) is currently the only available technique used in wafer polishing that achieves line widths of 0.25 µm or less as well as multilevel interconnections for dynamic memory and microprocessor applications.1-4
The CMP process is composed of a chemical effect from nanosize ceramic particles and a physical effect from the pressed pad. Pads and slurries are the consumables of a CMP process. The polishing pads consist of polyurethane. Generally two types of pads (hard and soft types) are simultaneously used in the CMP process. A hard pad gives better local (within die) planarity, but a soft pad gives better uniformity of material removal across the entire wafer. A hard pad is mounted onto a softer pad to form a stacked pad. Figure 15.1 shows a stacked CMP pad; the hard pad is the Rodel IC-1000 and the soft pad is the Rodel Suba-IV.5
