ABSTRACT
Due to continually shrinking feature sizes, higher clock frequencies, and the simultaneous growth in complexity, the role of interconnect as a dominant factor in determining circuit performance is growing in importance. The 2001 International Technology Roadmap for Semiconductors (ITRS) [1] shows that by 2010, high-performance integrated circuits (ICs) will count up to 2 billion transistors per chip and work with clock frequencies of the order of 10 GHz. Coping with electrical interconnects under these conditions will be a formidable task. Timing is already no longer the sole concern with physical layout: power consumption, cross talk, and voltage drop drastically increase the complexity of the trade-off problem. With decreasing device dimensions, it is increasingly difficult to keep wire propagation delays acceptable. Whereas dielectric constants below 2 (around 1.7-1.8) can be achieved using nanoporous silicon oxycarbide (SiOC)-like or organic (SiK-type) materials with an “air gap” integration approach, integration complexity is higher and mechanical properties are weaker. In addition, the use of ultra lowk materials is physically limited by the fact that no material permittivity can be less than 1 — that of
air. Thus, even with the most optimistic estimates for resistance-capacitance (RC) time constants using low-resistance metals, such as copper and low-k dielectrics, global interconnect performance required for future generations of integrated circuits (ICs) cannot be achieved with metal. Furthermore, because IC power dissipation is strongly linked to switching frequency, tomorrow’s architectures will require power over the 100-W mark to be able to operate in the 10-GHz range and above. At this level, thermal problems will jeopardize system performance if not strictly controlled.
