ABSTRACT
To achieve a high throughput usually means more power consumption in a given CMOS technology because the dynamic power consumption is proportional to the activity ratio. It implies that at a low activity ratio static logic circuits may consume less power compared with clocked dynamic logic circuits. For a given logic function, however, high-speed or a short-propagation delay does not necessarily mean high-power consumption, if highly efficient dynamic logic circuits with low power-delay products are used. Such low-power and very fast dynamic circuits are introduced in this chapter. A simple way to distinguish dynamic logic from static logic is to see whether the logic states are still correctly maintained, as for the static circuits, or destroyed, as for the dynamic circuits when the clock is turned off. This is because dynamic logic circuits need to be regularly refreshed for the charge stored on the logic nodes while static logic circuits need not.
