ABSTRACT
Over the last two decades, there has been a change in the drive for the continuous scaling of devices and circuits. Figure 17.1 plots the scaling dependence of different parameters.
The presented diagram is divided into two regions: constant-voltage scaling and constant-field scaling. The constant-voltage scaling timeframe reflects the period in which (C)MOS devices were still supplied by a constant voltage of 5 V. After a certain point in time (in the diagram: about 1997 for volume production) the supply voltage was reduced at the same pace as the transistor’s channel length, thereby keeping a constant field across the transistor channel: constant-field scaling. During the first period, in each new technology node, the average fabrication costs increased with a factor of
s
(about 1.2 times; s
≈
0.7), while the intrinsic speed improvement as obtained from the technology scaling was about a factor of
s
(
≈
2). In the same period, the power efficiency (= 1/
τ
D
-product: how much speed do I get per watt?) improved only by a factor of
s
(
≈
1.4). Therefore, the rise in fabrication costs could easily be compensated by the speed and density increase in that period.
