ABSTRACT
This chapter covers the area of early system-level power analysis and algorithmic-level power estimation. The techniques presented here shall enable the reader to understand the underlying concepts as well as the chances and limitations of tools, which shall guide the designers in optimizing the global system architecture for low power and help them selecting and further optimizing the algorithms to be implemented at lower levels. The figure of merit in reducing the power consumption by making the right decisions during this early phase covers several orders of magnitude. Just to illustrate the potential: there exist dozens of known and well-understood sorting algorithms. They all perform exactly the same task: take a set of objects and put them in an order according to the chosen sorting criterion. Despite the exactly same functional behavior, however, they all perform differently with respect to the computation time, memory usage, and the power consumption. Similarly, different algorithms with equivalent functionality are known for Fourier transform, compression, and many other functions, which are copiously used in mobile multimedia applications. Selecting the most power efficient one can be a product-differentiating factor.
