ABSTRACT
Design automation tools for analysis and optimization are key enablers for low-power design. With milliongate designs becoming commonplace and design sizes reaching the tens of millions mark, it is impossible to get a power-efficient implementation without appropriate automation. Automated optimization techniques are the fastest way to low-power design and, in fact, sometimes the only way for the highly complex chips of today. For optimization, a comprehensive set of register transfer level (RTL) and gate-level techniques are needed. These include clock gating, operand isolation, and many logic optimizations. In addition, several capabilities that allow both multi-threshold design and multi-voltage design are becoming increasingly important. A good analysis capability provides a basis for understanding the power needs of the design, identifying bottlenecks, and aiding in making correct decisions to reduce power. The power analysis tools need to provide a detailed, time-based power analysis capability for full chips.
